Invasive Tightly-Coupled Processor Arrays (B02)

TCPAs provide a platform for the highly time-predictable and ultra-low power implementation of parallel loop nests. Yet, as loop bounds may often be unknown at compile-time, new techniques for (a) self-invasion are required to determine claim sizes and perform (b) self-power adjustment and (c) self-selection of redundancy schemes at run time to enforce throughput, latency, power and reliability requirements. Moreover, to lift TCPAs to new application areas, (d) novel floating point processors with invadable precision (FloaTCPAs) including (e) functional units with programmable latency to compute instructions approximately will be investigated.