CoMap
Co-Design of Massively Parallel Embedded Processor Architectures
Schematische Darstellung einer Design Space Exploration
The CoMap project deals with the systematic (a) mapping, (b) evaluation, and (c) exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers.
The investigated class of computer architectures can be described by massively parallel networked processing elements which, using today's hardware technology, may be implemented on a single chip (SoC - System on a Chip).
Publikationen
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Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays
In: IEEE Embedded Systems Letters 3 (2011), p. 58-61
ISSN: 1943-0663
DOI: 10.1109/LES.2011.2124438
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Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays
In: Journal of Low Power Electronics 7 (2011), p. 29-40
ISSN: 1546-1998
DOI: 10.1166/jolpe.2011.1114
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Compilation Techniques for CGRAs: Exploring All Parallelization Approaches
International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS'10) (Scottsdale, AZ, 24. October 2010 - 29. October 2010)
In: Proc. 8th International Conference on Hardware-Software Codesign and System Synthesis 2010
DOI: 10.1145/1878961.1878995
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Modeling and synthesis of communication subsystems for loop accelerator pipelines
21st IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2010 (Rennes, 7. July 2010 - 9. July 2010)
In: Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) 2010
DOI: 10.1109/ASAP.2010.5540760
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Scheduling Techniques for High-Throughput Loop Accelerators (Dissertation, 2009)
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